The present invention relates to a technique of inspecting an electronic device and, more particularly, to a technique of fabricating and observing an electronic device, such as a semiconductor device, by using an ion beam.
In fabrication of electronic devices, such as a semiconductor memory (typified by a dynamic random access memory (DRAM)), a microprocessor, a semiconductor device, such as a semiconductor laser, and a magnetic head, manufacture at a high yield is demanded.
Reduction in the product yield due to occurrence of a defect causes deterioration in profitability. Consequently, it is a big task to discover a failure, a foreign matter, and poor processing as causes of a defect early and to take an early countermeasure. For example, at a manufacturing site of a semiconductor device, energies are put into early defect discovery by a careful inspection and analysis of the cause of the defect. In a process of fabricating actual electronic devices using a substrate, a completed substrate is inspected, the cause of an abnormal part, such as a defect in a circuit pattern or a foreign matter, is pursued, and a countermeasure is examined.
Usually, a high-resolution scanning electron microscope (hereinbelow, abbreviated as SEM) is used for observing a detailed structure of a sample. As the packing density of a semiconductor increases, it is becoming impossible to observe an object using the resolution of the SEM, and a transmission electron microscope (hereinbelow, abbreviated as TEM) having a higher observation resolution is used in place of the SEM.
Fabrication of a conventional sample for a TEM includes extracting a small piece from a sample by cleavage, cutting, or the like. In the case where a sample is a substrate, in most cases, the substrate has to be cut.
Recently, there is an example of using a processing method of irradiating a sample with an ion beam so that particles making up the sample are discharged from the sample by a sputtering action, that is, using a focused ion beam (hereinbelow, abbreviated as FIB) process.
According to the method, first, a rectangular-shaped pellet in the sub-millimeter range, including an area to be observed, is cut out from a sample, such as a substrate, by using a dicer, or the like. Subsequently, a part of the rectangular-shaped pellet is processed with an FIB so as to thin-out the film, thereby obtaining a TEM sample. The feature of the FIB-processed sample for TEM observation is that a part of the sample is thinned-out to a thin film having a thickness of about 100 nm so as to be able to be observed using the TEM. Although the method enables a desired observation part to be positioned with precision of a micrometer level and observed, the substrate still has to be cut.
As described above, although the advantage of monitoring a result of a process during fabrication of a semiconductor device or the like is big from the viewpoint of yield management, the substrate is cut in the fabrication of the sample as described above, and the piece of the substrate is not subjected to the following process, but is instead discarded. Particularly, in recent years, the diameter of wafers has increased in order to lower the unit price of fabricating a semiconductor device. To be specific, the number of semiconductor devices which can be fabricated from one wafer has increased, thereby reducing the unit price. However, the price of each wafer has increased, and the number of semiconductor devices which are lost by discarding a wafer has also increased. Therefore, the conventional inspection method that includes cutting of a wafer is very uneconomical.
Addressing this problem, there is a method capable of obtaining a sample without cutting a wafer. The method is disclosed in Japanese Patent Application Laid-Open No. 05-52721. According to the method, as shown in FIG. 2A, the posture of a sample 2 is kept so that the surface of the sample 2 is irradiated with an FIB 1 at a right angle, and a rectangular area in the surface of the sample 2 is scanned with the FIB 1, thereby forming a rectangular hole 101 having a required depth in the surface of the sample 2. As shown in FIG. 2B, the sample 2 is tilted and a bottom hole 102 is formed. The tilt angle of the sample 2 is changed by a specimen stage (not shown). Subsequently, the posture of the sample 2 is changed and, as shown in FIG. 2C, the sample 2 is set so that the surface of the sample 2 becomes perpendicular to the FIB 1 again, and a trench 103 is formed. A manipulator (not shown) is driven to make the tip of a probe 3 at the end of the manipulator come into contact with a part to be separated in the sample 2, as shown in FIG. 2D.
As shown in FIG. 2E, while supplying a deposition gas 5 from a nozzle 104 for delivering gas, an area including the tip portion of the probe 3 is locally irradiated with the FIB 1, thereby forming an ion beam gas assisted deposition layer (hereinbelow, simply called deposition layer 4). The separation part in the sample 2 and the tip of the probe 3 which are in contact with each other are connected by the deposition layer 4. As shown in FIG. 2F, the remaining part is cut with the FIB 1 and a micro sample 6 as a separate sample is cut out from the sample 2. The cut-out separate sample 6 is supported by the probe 3 connected as shown in FIG. 2G. The micro sample 6 is processed with the FIB 1 and an area to be observed is wall-processed, thereby obtaining a TEM sample (not shown).
As described above, the method is a method of separating a micro sample including a desired area to be analyzed from a sample, such as a wafer, by using the FIB process and means of carrying the micro sample. By introducing the micro sample separated by the method into various analyzers, analysis can be made.
The method of cutting out a micro sample for inspection from a sample without cutting a wafer and allowing the wafer to be continuously subjected to the following process is disclosed in Japanese Patent Application Laid-Open No. 2000-156393. According to this method, there is no semiconductor device which is lost when a wafer is cut, so that total fabrication cost of semiconductor devices can be reduced.
In fabrication of electronic devices as described above, in the case of allowing the wafer to be subjected to the next process, a process for forming hole from which the micro sample is taken out is necessary. In other words, when the formed hole is not processed, the following problems occur.
(1) An end of the hole is broken off and becomes a contamination source. (2) The hole causes an uneven shape of the wafer at the time of spin coating, polishing, or the like. (3) Dusts gather in the hole. For example, in the case of performing CMP (Chemical & Mechanical Polishing) after taking out a micro sample, CMP grains enter the hole and all of these grains cannot be taken away by cleaning. In any processes after performing CMP, a CMP grain can come out of the hole and become foreign matter or cause impurity contamination, which fluctuates device characteristics.
A method related to the technique of putting a wafer subjected to an FIB process back into a process line is disclosed in Japanese Patent Application Laid-Open No. 6-260129. According to this method, in order to put a sample irradiated with a focused ion beam using gallium as an ion source back into a process, either a part to which gallium has been implanted is removed by using an ion beam of a gaseous element which does not exert a conspicuous influence on the characteristics of a sample, or an organic metal film is deposited using an energy beam so as to cover a portion in which gallium is implanted. Specifically, an area to be processed and observed is cleaned by using any of argon, oxygen ions, and oxygen radicals, a compound is deposited and, after that, the sample is put back into the fabrication process.
In an instrument of the method, however, Ga contamination is considered, but a process for addressing an opened hole is not considered.
A method related to the technique of putting a wafer back into a process line after a cross section inspection is disclosed in Japanese Patent Application Laid-Open No. 10-116872. In the disclosed method, a cross section of a wafer is inspected during a semiconductor device process. A hole opened for obtaining the section is filled with an insulator or a conductive film by energy-beam-induced CVD (Chemical Vapor Deposition, although a technical term of CVD is conventionally used, gas-assisted deposition is used as a synonym), or is filled with a desired film by applying a liquid material and irradiating the material with an energy beam. The wafer is put back to a fabrication process line, and the fabrication is continued. Particularly, it is disclosed that a wafer is taken out, a cross section inspection is performed, and the inspected part in the wafer is planarized with an ion beam.
International Publication Number WO 99/17103 discloses a method of covering a hole opened with an FIB with a dielectric by using an ion beam.
However, the conventional hole filling method after the FIB process has the following problems.
First, in the case of filling a hole by the energy-beam-induced gas-assisted deposition, the following problems occur depending on the kinds of beams.
(1) In the case of forming a film by applying a liquid material and irradiating the material with an energy beam, when a film is thick, a crack occurs in the film in a process of irradiating the material with the energy beam. If the wafer is subjected to the following process, it is feared that a piece from the crack can disperse and cause a defect. The depth of an opened hole from which a micro sample is taken out is generally at least 3 to 5 micrometers. On the other hand, the thickness of a film which can be formed without a crack from an oxide film material which is generally used as the liquid material is at most 1 to 2 micrometers. A crack can occur during a heating process in an oxide film applied thicker than that. (2) In laser-beam-induced gas-assisted deposition, a film grows isotropically, so that it is difficult to fill a hole so that the surface is flat. (3) In argon ion beam induced gas-assisted deposition, the beam size in an inexpensive ion emitting system is generally 50 to 500 micrometers. On the other hand, the size of a hole is at most 20 micrometers. It is therefore difficult to form a film only in the hole, but instead a film is formed not only in the hole but also over the periphery of the hole. Thus, it is difficult to fill the hole while realizing a flat surface. (4) In electronic beam induced gas-assisted deposition, deposition speed is generally low and it is difficult to fill the hole within practical time such as within 10 minutes.
(5) In gallium FIB induced gas assisted deposition, a deposition layer can be formed in the hole, but there is a problem such that gallium is taken into the deposition layer. Further, by a sputtering action by FIB irradiation, pieces of gallium and a sample are spread also to areas other than the FIB processed area. The possibility of the gallium contamination causing defects in the fabrication of semiconductor devices is high. Specifically, when nothing is done to address the contamination, and the wafer is subjected to the following process, gallium is diffused and enters a semiconductor device when subjected to the fabrication process, and problems such as poor electric characteristics and poor contacts occur. From the viewpoint of filling a hole at high speed, although the speed is faster as compared with the electron beam induced gas-assisted deposition, it is still difficult to fill the hole within a practical time, such as 10 minutes. Since the absolute amount of a deposition layer can be increased in proportion to an FIB current, then in order to increase the speed of filling a hole, the FIB current is increased. However, when the FIB current is increased to a high current of about 1 nA or higher, the deposition layer forming efficiency deteriorates. The deposition amount and the sputtering amount become almost equal to each other, so that growth of the deposition layer is stopped and a hole cannot be filled at high speed.
Consequently, for improvement in the yield of a semiconductor device and the like, to conduct an inspection during a process without cutting a wafer, the following techniques are demanded, such as a technique of filling at high speed a hole from which a micro sample has been taken out or a hole opened for inspecting a section, while achieving surface flatness. It is also demanded to establish a hole filling method by which a foreign matter is not generated and gallium contamination does not cause a defect in a semiconductor device, so that a problem does not occur in the subsequent processes, and to develop an apparatus capable of realizing the method.
Particularly, from the viewpoint of putting an inspected wafer back into a fabrication line, it is important to shorten the time required to inspect the wafer and put the wafer back into the fabrication line. In other words, a technique for increasing the speed of filling a hole is demanded, and the conventional methods do not address this demand. For example, a technique is desired that is capable of filling a hole at high speed with an increased deposition amount, and without deteriorating a deposition layer forming efficiency, even when the FIB current is increased, specifically, to a high current of about 1 nA or higher.